The present invention relates to apparatus and methods for testing semiconductor electrical devices, particularly memory devices.
Testing is performed on semiconductor devices to locate defects and failures in such devices, typically occurring during the manufacture of the semiconductor devices. As circuit density on semiconductor devices increases, the number of defects and failures can increase. Semiconductor manufacturers, therefore, have an increasing need to detect defects and failures in semiconductor devices as circuit density increases.
Thus, for quality control and to improve yields of semiconductor devices, semiconductor devices are tested, often before a die containing the semiconductor device is packaged into a chip. A series of probes on a test station electrically contact pads on each die in a wafer to access portions of the individual semiconductor devices on the die. For example, in a semiconductor memory device, the probes contact address pads and data input/output pads to access selected memory cells in the memory device. Typical dynamic random access memory devices (xe2x80x9cDRAMxe2x80x9d) include one or more arrays of memory cells that are each arranged in rows and columns. Each array of memory cells includes word or row lines that select memory cells along a selected row, and bit or column lines (or pairs of lines) that select individual memory cells along a row to read data from, or write data to, the cells in the selected row.
During testing, predetermined data or voltage values are typically written to selected row and column addresses that correspond to certain memory cells, and then the voltage values are read from those memory cells to determine if the read data matches the data written to those addresses. If the read data does not match the written data, then the memory cells at the selected addresses likely contain defects and the semiconductor device fails the test.
Nearly all semiconductor devices, particularly memory devices, include redundant circuitry on the semiconductor device that can be employed to compensate for certain detected failures. As a result, by enabling such redundant circuitry, the device need not be discarded even if it fails a particular test. For example, memory devices typically employ redundant rows and columns of memory cells so that if a memory cell in a column or row of the primary memory array is defective, then an entire row or column of redundant memory cells can be substituted therefor, respectively.
Substitution of one of the spare rows or columns is conventionally accomplished by opening fuses (or closing antifuses) in a row or column decoder on the die. Conventional fuses include polysilicon fuses which can be opened by a laser beam, and also avalanche-type fuses and antifuses. If a given row or column in the array contains a defective memory cell, then the wafer can be moved to another station where a laser blows a fuse to enable a redundant row or column. The redundant row or column is then accessed simply providing the address to a row of address decoder that substitutes the appropriate redundant row/column for the defective row or column in the primary memory array.
The rows and columns of redundant memory cells, as well as the primary memory cells, must be tested. During the testing process, additional pads are provided on the die so that probes on the test station can write data to and read data from these redundant rows and columns.
A semiconductor device can be most thoroughly tested when the device is still in die form on the semiconductor wafer. The series of tests performed on the semiconductor device while in die form are typically performed in a sequential manner where initial tests attempt to weed out dies that may fail under future tests. These dies are typically discarded as being fatally defective at an early stage because it is time-intensive, and therefore expensive, to thoroughly test such dies if initial test results of the die conclude that the device will likely fail. Furthermore, it is even more expensive to prepare and package a die into a chip. As a result, it is desirable to determine at an early stage which dies will fail as acceptable packaged chips.
For example, if the test of the die shows that some of the redundant rows and columns contain defects, then the die may be discarded since more thorough testing downstream may indicate failures for which an insufficient number of redundant elements can be employed. Therefore, the decision is made to mark a given die as defective, and therefore not incur the expense of preparing, packaging and testing the chip which will likely fail during downstream testing. A small margin of devices, however, could pass future tests, and therefore be commercially acceptable (e.g., only a few defects on the device are discovered and therefore only a few redundant rows/columns are necessary). Therefore, it would be desirable to package and test nearly every die to thereby produce a greater number of commercially acceptable chips. However, packaged chips cannot be as thoroughly tested as unpackaged dies in wafer form. Therefore, it would be desirable to be able to fully test packaged chips in the same manner as unpackaged dies.
Another drawback of testing semiconductors in wafer form is that semiconductor wafers are often difficult to manipulate, and typically require a test bed or other apparatus to releasably secure the wafer while the probes are moved to contact the pads on each die. Additionally, moving the wafer from one test station to another (e.g., to a second station having a laser for blowing fuses), adds to the time-consuming nature of testing semiconductor devices in die form. Overall, the testing of semiconductor devices in die form is time consuming. Therefore, semiconductor manufacturers desire to test a given semiconductor device after it has been packaged as a semiconductor chip, because the chip can be automatically inserted into a test socket using pick and place machinery. Automated testing circuitry can then apply predetermined voltages and signals to the chip, write test patterns thereto, and analyze the results therefrom to detect for failures in the chip.
Often, the number of pads on a die is greater than the number of pins on the packaged semiconductor chip. Therefore, as noted above, certain tests performed while the semiconductor device is in die form cannot be performed on the device after it has been packaged. For example, redundant rows/columns can be directly accessed when the device is in die form, but not when packaged into a chip. As a result, packaged chips necessarily undergo less rigorous testing than unpackaged dies. Packaged chips can include manufacturing defects that are not yet failures and thus are undetectable by the limited number of tests capable of being performed on the packaged chips.
To provide for rapid testing of chips, and to compensate for the limitation on the number of pads accessible in a packaged chip, manufacturers currently employ on chip test mode circuitry that initiates a special test mode when a predetermined combination of signals or xe2x80x9ctest key vectorxe2x80x9d signals are applied to the pins of the chip. For example, external test circuitry can force a low value to a write enable pin WE before signals applied to column address select (xe2x80x9cCASxe2x80x9d) pin and row address select (xe2x80x9cRASxe2x80x9d) pin fall to a low value. The test key vector signals applied to the pins are preferably selected to be signals not normally applied to such pins by a user under normal operation of the chip, and therefore, a user would not accidentally enter the test mode for the chip. To further ensure that a user does not accidentally enter into a test mode for the chip, a continuous supervoltage (e.g., 10 volts) must be applied to a pin on the chip to enter the test mode. Such a supervoltage is one beyond the normal tolerances for the chip and therefore would not normally be applied to the chip by a user under normal conditions.
For example, the redundant rows/columns can be accessed by applying a certain test key vector signal and a supervoltage to the chip, which allows the chip to enter into a particular test mode. The redundant rows and columns can then be tested while the die is in its packaged chip form, even though a particular pad on the die is not directly accessible.
While it is desirable to test the redundant rows and columns after the die has been packaged as a chip, the currently known methods for accessing and testing the redundant rows/columns is time-consuming. External testing circuitry, after accessing and testing the rows and columns of cells in the primary memory array, must apply a new test key vector signal and supervoltage of the chip to access the redundant rows and columns. The need to apply the test key vector signal and supervoltage adds additional steps during the testing process which necessarily increases the time required to test the chip.
Additionally, current memory devices divide the primary array of memory cells into sub-arrays, or blocks, so that only a portion of the memory need be energized in a given access, resulting in significant power reduction. As the number of sub-arrays or blocks increases, e.g., up to 16 or 32 blocks, each block typically includes its own redundant rows and columns. As a result, conventional testing of the redundant rows and columns requires the external testing circuitry to frequently enter into and out of the special test mode for accessing the various redundant rows/columns. In other words, the external test circuitry must frequently and repeatedly apply the test key vector signal and supervoltage for each redundant row and column in the multiple blocks, which thereby further increases the time-consumptive nature of such testing.
The present invention allows rows and columns of redundant elements in packaged semiconductor chips, such as DRAMs and other semiconductor memory devices, to rapidly undergo testing when in packaged form, where such testing previously had been available only under time-consuming processes. During testing, addresses are typically compressed or multiplexed so that a single address can access multiple locations in a memory array and thereby allow data to be written and read from multiple locations using a reduced size address word. As a result, where an 11-bit address word is typically required to access a particular memory cell in the array, under compression testing, only a 9- or 10-bit test address is used to access multiple memory cells. By employing a reduced bit address word, one or more address pins are unused during the compression testing.
A redundant element access circuit on the die with the memory device is coupled to the one or more unused address pins. The access circuit receives a control signal that allows external testing circuitry to select between the primary memory array and the redundant rows and columns. Therefore, during compressed address mode testing, a full 11-bit word is employed by the testing circuitry to test both the primary memory array and the redundant rows and columns, where two of the 11 bits select between the primary memory array and the redundant rows and/or columns, while the remaining bits are the typical compressed test address. No supervoltage or test key vector signal is required to initiate a new testing mode to access the redundant rows/columns. Rather, a simple address word, as is typically employed, is modified to access and thereby test the redundant rows and columns. As a result, the present invention allows both primary and redundant elements such as memory cells to be rapidly tested in a packaged chip. Since packaged chips can be tested in parallel, using automated equipment, as opposed to testing in die form, the present invention provides a tremendous time saving step during the testing of semiconductor devices.
In a broad sense, the present invention embodies a semiconductor device having a die and a plurality of terminals. The terminals include access terminals for receiving access signals. The semiconductor device includes a semiconductor circuit, control and access circuitry, and a redundant element access circuit.
The semiconductor circuit is formed on the die and has a plurality of primary circuit elements and a plurality of redundant circuit elements. The plurality of primary and at least some of the redundant circuit elements are addressable by electrically conductive lines based on an access word applied to the access terminals.
The control and access circuitry is coupled to the terminals and to the electrically conductive lines for permitting communication with the plurality of primary and redundant circuit elements. The redundant element access circuit is coupled to the control and access circuitry and to at least one of the access terminals. The redundant element access circuit receives an externally applied element select signal that is applied to the at least one of the access terminals. The redundant element access circuit outputs a redundant element select signal to allow the control and access circuitry to access at least one of the plurality of redundant elements in response thereto.
The present invention also embodies a computer system having an input device, an output device, an address bus, a data bus, a set of control lines, a memory controller, a processor, and a memory device. The memory controller is coupled to the address and data buses and to the set of control lines. Similarly, the processor is coupled to the input and output devices, and to the address and data buses and to the set of control lines. The memory device is coupled to the memory controller through the address and data buses and the set of control lines.
The memory device includes a memory circuit formed on a die having terminals including address terminals coupled to the address bus. The memory circuit has a plurality of primary memory cells and a plurality of redundant memory cells. The plurality of primary and at least some of the redundant memory cells are addressable by electrically conductive lines based on an address word applied to the address terminals. The address word has a predetermined bit length. Control and address circuitry is coupled to the terminals and to the electrically conductive lines for permitting communication with the plurality of primary and redundant memory cells. A redundant element access circuit is coupled to the control line address circuitry and to at least one of the address terminals, so as to receive an externally applied element select signal applied to the at least one of the address terminals. The redundant element access circuit outputs a redundant element access signal to allow the control address circuitry to access at least some of the plurality of redundant elements.
The present invention solves problems inherent in the prior art of semiconductor testing and provides additional benefits by allowing rapid testing to be performed on redundant elements in packaged semiconductor chips. As a result, the present invention avoids many of the drawbacks of testing unpackaged devices in die form. Other features and advantages of the present invention will become apparent from studying the following detailed description of the presently preferred embodiment, together with the following drawings.